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19-3026; Rev 0; 10/03
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector
General Description
The MAX3645 limiting amplifier functions as a data quantizer and is pin compatible with the Mindspeed MC2045-2 and MC2045-2Y postamplifiers. The amplifier accepts a wide range of input voltages and provides constant-level positive emitter-coupled logic (PECL) output voltages with controlled edge speeds. The MAX3645 features an integrated power detector with complementary PECL loss-of-signal (LOS) outputs that indicate when the input power level drops below a programmable threshold. An optional squelch function holds the data outputs at static levels during a LOS condition. The MAX3645 operates from a single +3.3V or +5.0V power supply over a -40C to +85C temperature range. It is available in 16-pin SO and 16-pin QSOP packages.
Features
o Pin Compatible with the Mindspeed MC2045-2/MC2045-2Y o 500V Input Sensitivity (BER = 10-12) o Compatible with 4B/5B Data Coding o Programmable LOS Threshold o o o o Stable LOS Threshold Over Supply Range Output Disable Function and Automatic Squelch Single +3.3V or +5.0V Power Supply 18mA Supply Current
MAX3645
Ordering Information
PART MAX3645ESE MAX3645EEE TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 16 SO 16 QSOP
Applications
SONET 155Mbps Transceivers Fast Ethernet Receivers FDDI 125Mbps Receivers FTTx Receivers ESCON Receivers
TOP VIEW
CAZ2 1 CAZ1 2 GNDA 3 DIN+ 4 DIN- 5 VCCA 6 CSD 7 DIS 8
Pin Configuration
16 TH 15 N.C. 14 VCCE
MAX3645
13 DOUT+ 12 DOUT11 GNDE 10 LOS 9 LOS
SO/QSOP
Typical Application Circuit
VCC VCC VCC PIN K OUT+ 0.1F DIN+ CSD 1nF CSD VCCA CAZ1 CAZ2 VCCE N.C. DOUT+ CAZ 0.1F VCC
MAX3644*
IN GND
MAX3645
OUT0.1F DINGNDA TH
DOUTLOS GNDE 50 50 50
DIS
RTH 100
LOS
50 VCC - 2V
*FUTURE PRODUCT VCC - 2V
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector MAX3645
ABSOLUTE MAXIMUM RATINGS
Power-Supply Voltage (VCCA, VCCE) ....................-0.5V to +7.0V Voltage at CAZ1, CAZ2, DIN+, DIN-, CSD, DIS, TH ................................-0.5V to (VCC + 0.5V) PECL Output Current (DOUT+, DOUT-, LOS, LOS) ...........50mA Differential Voltage between CAZ1 and CAZ2......-1.5V to +1.5V Differential Voltage between DIN+ and DIN- ........-1.5V to +1.5V Continuous Power Dissipation (TA = +85C) 16-Pin SO (derate 8.7mW/C above +85C)................565mW 16-Pin QSOP (derate 8.3mW/C above +85C)...........540mW Storage Ambient Temperature Range (TS).......-65C to +160C Lead Temperature (soldering, 10s)..............................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = +2.97V to +5.5V, PECL outputs are terminated with 50 to VCC - 2V, RTH = 100, CAZ = 0.1F, CSD = 1nF, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER POWER SUPPLY Supply Current INPUT SPECIFICATIONS Input Resistance Input Sensitivity (Note 1) Input Overload (Note 1) Input-Referred Offset Voltage Input Common-Mode Voltage Input-Referred RMS Noise DIS Input High DIS Input Low DIS Input Current OUTPUT SPECIFICATIONS PECL Output-Voltage High PECL Output-Voltage Low Data Output Transition Time Pulse-Width Distortion t R , tF PWD (Notes 1, 2) (Notes 1, 2) 20% to 80% (Notes 1, 2, 4) (Notes 1, 2, 4, 5) VCC 1085 VCC 1830 0.7 30 VCC 880 VCC 1555 1.4 200 mV mV ns ps VCMM VIN-NOISE VIH VIL IIL, IIH (Notes 2, 3) PECL or CMOS logic PECL or CMOS logic 0V VDIS VCC VCC 1160 0 -10 RIN VIN-MIN VIN-MAX Single ended; VIN = 200mV Single ended Differential Single ended Differential Unterminated input, output offset divided by DC gain (Note 2) 750 1500 2 VCC 0.87 36 50 VCC VCC 1480 +10 40 3.3 4.8 6.4 0.5 1.0 k mVP-P mVP-P V V VRMS mV mV A ICC Excludes PECL termination currents 18 27 mA SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector
ELECTRICAL CHARACTERISTICS (continued)
(VCC = +2.97V to +5.5V, PECL outputs are terminated with 50 to VCC - 2V, RTH = 100, CAZ = 0.1F, CSD = 1nF, TA = -40C to +85C. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER TRANSFER CHARACTERISTICS Bandwidth Low-Frequency Cutoff Gain = 60dB CAZ = open CAZ = 0.1F 0 RTH 2k 10log (VDEASSERT/VASSERT) (Note 7) RTH = 0, low setting LOS Assert Level RTH = 1k, medium setting RTH = 2k, high setting RTH = 0, low setting LOS Deassert Level Signal-Dectect Filter Resistance RSD RTH = 1k, medium setting RTH = 2k, high setting Pin 7 2 1.4 2.3 0.5 4.8 12 1.1 8.0 20 14 0.9 6.6 17 1.5 10.8 28 20 2 80.0 1.3 8.3 22 1.9 13.5 36 26 k mVP-P mVP-P 150 250 500 0.5 20 MHz kHz SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX3645
LOSS-OF-SIGNAL SPECIFICATIONS (Notes 2, 4, 6) LOS Sensitivity Range LOS Hysteresis LOS Assert/Deassert Time mVP-P dB s
Note 1: Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
Between sensitivity and overload, the output amplitude is >95% of the fully limited amplitude and all AC specifications are met. Guaranteed by design and characterization. Noise is derived from BER measurement. The data input transition time is controlled by a 4th-order Bessel filter with f-3dB = 0.75 x data rate. PWD = [(width of wider pulse) - (width of narrower pulse)] / 2, measured with 155Mbps 0011 pattern. All LOS specifications are measured using a 155Mbps 223 - 1 PRBS pattern. The signal at the input is switched between two amplitudes, SIGNAL_ON and SIGNAL_OFF, as shown in Figure 1.
VIN SIGNAL ON 1dB MAXIMUM DEASSERT LEVEL
6dB
MAXIMUM POWER-DETECT WINDOW
MINIMUM ASSERT LEVEL
0V
SIGNAL OFF
TIME
Figure 1. Signal Levels for LOS Assert/Deassert Time Measurement _______________________________________________________________________________________ 3
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector MAX3645
Typical Operating Characteristics
(VCC = 3.3V, PECL outputs terminated with 50 to VCC - 2V, RTH = 100, CAZ = 0.1F, CSD = 1nF, TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. TEMPERATURE (EXCLUDES PECL OUTPUT CURRENTS)
45 40 SUPPLY CURRENT (mA) 35 30 25 20 15 10 5 -40 -15 10 35 60 85 VCC = 3.3V VCC = 5.0V 200mV/ div
MAX3645 toc01
OUTPUT EYE DIAGRAM (VIN = 1mVP-P, 155Mbps, 223 - 1PRBS)
MAX3654 toc02
OUTPUT EYE DIAGRAM (VIN = 1500mVP-P, 155Mbps, 223 - 1PRBS)
MAX3645 toc03
50
200mV/ div
1ns/div
1ns/div
TEMPERATURE (C)
TRANSFER FUNCTION
MAX3654 toc04
BIT-ERROR RATIO vs. DIFFERENTIAL INPUT VOLTAGE
10
-4
INPUT-REFERRED RMS NOISE vs. TEMPERATURE
85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 -40
MAX3645 toc05 MAX3645 toc06
2000 DIFFERENTIAL OUTPUT VOLTAGE (mVP-P) 1800 1600 1400 1200 1000 800 600 400 0.01 0.1 1 10 RTH = 1k RTH = 2k RTH = 0 RTH = 100
10-3 155Mbps, 223 - 1 PRBS
10-5 BIT-ERROR RATIO 10-6 10-7 10-8 10-9 10-10 10-11 10-12
INPUT-REFERRED NOISE (VRMS)
VCC = +5.0V
VCC = +3.3V
100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
-15
10
35
60
85
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
TEMPERATURE (C)
SMALL-SIGNAL GAIN vs. RTH
MAX3645 toc07
LOSS-OF-SIGNAL THRESHOLD vs. RTH (VCC = +3.3V AND +5.0V)
30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 0
MAX3645 toc08
LOSS-OF-SIGNAL HYSTERESIS vs. TEMPERATURE
3.0 10log (DEASSERT/ASSERT) (dB) 2.8 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 RTH = 100 RTH = 1k RTH = 2k 155Mbps, 223 - 1 PRBS
MAX3645 toc09
100 90 80 20log (VOUT/VIN) (dB) 70 60 50 40 30 20 10 0 0 0.2 0.5 0.7 1.0 RTH (k) 1.2 1.5 1.7 VIN = 0.1mVP-P
3.2
155Mbps, 223 - 1 PRBS
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
LOS DEASSERT
LOS ASSERT
2.0
0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 RTH (k)
-40
-15
10
35
60
85
TEMPERATURE (C)
4
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+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector
Typical Operating Characteristics (continued)
(VCC = 3.3V, PECL outputs terminated with 50 to VCC - 2V, RTH = 100, CAZ = 0.1F, CSD = 1nF, TA = +25C, unless otherwise noted.)
MAX3645
LOSS-OF-SIGNAL WITH SQUELCH (155Mbps, 223 - 1PRBS)
MAX3654 toc10
PULSE-WIDTH DISTORTION vs. DIFFERENTIAL INPUT VOLTAGE
155Mbps 0011 PATTERN 90 PULSE-WIDTH DISTORTION (ps)
MAX3645 toc11
100
VIN
80 70 60 50 40 30 20 10 0
VOUT
LOS 10s/div
0.1
1
10
100
1000
10,000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
DATA OUTPUT TRANSITION TIME vs. DIFFERENTIAL INPUT VOLTAGE
MAX3645 toc12
3.0 2.5 TRANSITION TIME (ns) 2.0 1.5 1.0 0.5 0 0.1 1 10 100 1000
10,000
DIFFERENTIAL INPUT VOLTAGE (mVP-P)
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+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector MAX3645
Pin Description
PIN MINDSPEED MC2045-2 MC2045-2Y PIN NAME CAZMAXIM MAX3645 PIN NAME FUNCTION
1
CAZ2
Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ1 sets the time constant of the offset correction loop. The offset correction is disabled when the CAZ1 and CAZ2 pins are shorted together. Offset-Correction-Loop Capacitor Connection. A capacitor connected between this pin and CAZ2 sets the time constant of the offset correction loop. The offset correction is disabled when the CAZ2 and CAZ1 pins are shorted together. Analog Supply Ground. Must be at the same potential as the GNDE pin. Positive Data Input Negative Data Input +2.97V to +5.5V Analog Supply Voltage. Must be at same potential as the VCCE pin. Signal-Detect-Filter Capacitor Connection. Connect the CSD capacitor between CSD and VCCA. Disable Input, PECL or CMOS Compatible. Data outputs are held to a static logic 0 when DIS is asserted high. The LOS function remains active when the outputs are disabled. When connected to the LOS pin, an automatic squelch function is enabled. Positive Loss-of-Signal Output, PECL. LOS is high when the level of the input signal drops below the threshold set by the TH input. LOS is low when the signal level is above the threshold. LOS can be connected directly to DIS for automatic squelch. Negative Loss-of-Signal Output, PECL. LOS is low when the level of the input signal drops below the threshold set by the TH input. LOS is high when the signal level is above the threshold. Digital Supply Ground. Must be at the same potential as the GNDA pin. Negative Data Output, PECL. A high at DIS forces DOUT- high. Positive Data Output, PECL. A high at DIS forces DOUT+ low. +2.97V to +5.5V Digital Supply Voltage. Must be at the same potential as the VCCA pin. No Connection Loss-of-Signal Threshold Pin. Resistor (RTH) to ground sets the LOS threshold. This pin cannot be left open.
2 3 4 5 6 7 8
CAZ+ GNDA DIN DIN VCCA CF JAM
CAZ1 GNDA DIN+ DINVCCA CSD DIS
9
ST
LOS
10 11 12 13 14 15 16
ST GNDE DOUT DOUT VCCE NC VSET
LOS GNDE DOUTDOUT+ VCCE N.C. TH
Detailed Description
The MAX3645 consists of gain stages, offset correction, power detector, LOS indicators, and PECL output buffers. See Figure 2 for the functional diagram.
tance variation (3.3k to 6.4k) must be considered to accurately calculate the -3dB frequency. Capacitor values should be chosen that set the -3dB frequency at least a factor of 10 below the lowest frequency of interest. A capacitor value of 0.1F is recommended.
Data Input
The data inputs have a single-ended input resistance of 4.8k and are internally DC-biased to VCC - 0.87V (see Figure 3). External capacitors are required to AC-couple the data signals. Pattern-dependent jitter is minimized by using coupling capacitor values large enough to pass the lowest frequencies of interest (consecutive ones and zeros) with the given input resistance. Typically, 0.1F coupling capacitors yield a -3dB frequency of 354Hz. Capacitor tolerance and input resis6
Gain Stage and Offset Correction
The limiting amplifier provides approximately 74dB (RTH = 100) of gain. This large gain makes the amplifier susceptible to small DC offsets in the signal path. To correct DC offsets, the amplifier has an internal feedback loop that acts as a DC autozero circuit. By correcting the DC offsets, the limiting amplifier improves receiver sensitivity and power-detector accuracy.
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+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector MAX3645
TH CSD
VCC VCC
LOS LOS POWER DETECTOR
VCC - 0.87V
4.8k
4.8k
MAX3645
DOUT+ DOUTDIS
DIN+ DIN-
DIN+
OFFSET CORRECTION CINT
DINESD STRUCTURES
CAZ1
CAZ2
Figure 2. Functional Diagram
Figure 3. Equivalent Data Input Circuit
The external autozero capacitor (CAZ), in parallel with internal capacitance (CINT), determines the time constant of the DC offset correction loop. With CAZ = 0.1F (recommended), the -3dB frequency cutoff of the signal path is typically 0.5kHz.
detector time constant, which determines the LOS assert/deassert time. With C SD = 1nF the assert/ deassert time is in the range of 2.3s to 80s. This provides a long enough time constant to avoid false triggering due to variations in mark density.
Power Detector and LOS Indicators
The external resistor RTH sets the gain of the first limiting stage. This gain setting controls the threshold at which the power detector indicates an LOS condition. Power detection is accomplished by rectifying and lowpass filtering the data signal, then comparing it to the programmed threshold voltage. A hysteresis of 2dB prevents the LOS output from chattering when the input signal is near the threshold.
Disable Function
When the DIS input is forced high, the disable function is enabled, which holds DOUT+ low and DOUT- high. The disable function is used to prevent the data outputs from toggling due to noise when no signal is present. The LOS output can be connected to the DIS input for automatic squelch.
PECL Output Terminations
The proper termination for a PECL output is 50 to (VCC - 2V), but other standard termination techniques can be used. For more information on PECL terminations and how to interface with other logic families, refer to Maxim Application Note HFAN-01.0: Introduction to LVDS, PECL, and CML.
PECL Output Buffer
The data outputs (DOUT+, DOUT-) and the loss-of-signal outputs (LOS+, LOS-) are PECL outputs. The equivalent PECL output circuit is shown in Figure 4.
Applications Information
Programming LOS Assert/Deassert Levels
The appropriate value of RTH is determined by using the Loss-Of-Signal Threshold vs. R TH graph in the Typical Operating Characteristics.
Layout Considerations
For best performance, use good high-frequency layout techniques. Filter power supplies, keep ground connections short, and use multiple vias where possible. Power-supply decoupling should be placed close to the VCC pins. Minimize the distance from the preamplifier and use controlled-impedance transmission lines to interface with the outputs when possible.
LOS Time Constant
The lowpass filter of the power detector comprises a 20k on-chip resistor (RSD) and an external capacitor (CSD). The CSD capacitor value determines the power-
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7
+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector MAX3645
Chip Information
VCC
TRANSISTOR COUNT: 1026 PROCESS: Silicon bipolar
DOUT+/LOS DOUT+/LOS ESD STRUCTURES
Figure 4. Equivalent PECL Output Circuit
8
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+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
SOICN .EPS
MAX3645
INCHES DIM A A1 B C e E H L MAX MIN 0.069 0.053 0.010 0.004 0.014 0.019 0.007 0.010 0.050 BSC 0.150 0.157 0.228 0.244 0.016 0.050
MILLIMETERS MAX MIN 1.35 1.75 0.10 0.25 0.35 0.49 0.19 0.25 1.27 BSC 3.80 4.00 5.80 6.20 0.40 1.27
N
E
H
VARIATIONS:
1
INCHES
MILLIMETERS MIN 4.80 8.55 9.80 MAX 5.00 8.75 10.00 N MS012 8 AA 14 AB 16 AC
TOP VIEW
DIM D D D
MIN 0.189 0.337 0.386
MAX 0.197 0.344 0.394
D C
A e B A1
0 -8 L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL DOCUMENT CONTROL NO. REV.
21-0041
B
1 1
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+2.97V to +5.5V, 125Mbps to 200Mbps Limiting Amplifier with Loss-of-Signal Detector MAX3645
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
QSOP.EPS
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
21-0055
E
1 1
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
10 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2003 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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